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00024 #include "config.h"
00025 #include "ctrl_access.h"
00026
00027
00028
00029
00030 #if (ACCESS_MEM_TO_MEM == ENABLED)
00031 #include "modules/file_system/fat.h"
00032 U8 buf_sector[FS_SIZE_OF_SECTOR];
00033 #endif
00034
00035
00037
00038
00039
00040
00041
00042 #ifndef LUN_0
00043 # error LUN_0 must be defined with ENABLE or DISABLE in conf_access.h
00044 #endif
00045 #ifndef LUN_1
00046 # error LUN_1 must be defined with ENABLE or DISABLE in conf_access.h
00047 #endif
00048 #ifndef LUN_2
00049 # error LUN_2 must be defined with ENABLE or DISABLE in conf_access.h
00050 #endif
00051 #ifndef LUN_3
00052 # error LUN_3 must be defined with ENABLE or DISABLE in conf_access.h
00053 #endif
00054 #ifndef LUN_4
00055 # error LUN_4 must be defined with ENABLE or DISABLE in conf_access.h
00056 #endif
00057 #ifndef LUN_5
00058 # error LUN_5 must be defined with ENABLE or DISABLE in conf_access.h
00059 #endif
00060 #ifndef LUN_6
00061 # error LUN_6 must be defined with ENABLE or DISABLE in conf_access.h
00062 #endif
00063 #ifndef LUN_7
00064 # error LUN_7 must be defined with ENABLE or DISABLE in conf_access.h
00065 #endif
00066 #ifndef LUN_USB
00067 # error LUN_USB must be defined with ENABLE or DISABLE in conf_access.h
00068 #endif
00069
00070
00071
00072 #if (LUN_0 == ENABLE)
00073 #define LUN_0_EN 1
00074 U8 code lun0_name[]=LUN_0_NAME;
00075 #else
00076 #define LUN_0_EN 0
00077 #endif
00078 #if (LUN_1 == ENABLE)
00079 #define LUN_1_EN 1
00080 U8 code lun1_name[]=LUN_1_NAME;
00081 #else
00082 #define LUN_1_EN 0
00083 #endif
00084 #if (LUN_2 == ENABLE)
00085 #define LUN_2_EN 1
00086 U8 code lun2_name[]=LUN_2_NAME;
00087 #else
00088 #define LUN_2_EN 0
00089 #endif
00090 #if (LUN_3 == ENABLE)
00091 #define LUN_3_EN 1
00092 U8 code lun3_name[]=LUN_3_NAME;
00093 #else
00094 #define LUN_3_EN 0
00095 #endif
00096 #if (LUN_4 == ENABLE)
00097 #define LUN_4_EN 1
00098 U8 code lun4_name[]=LUN_4_NAME;
00099 #else
00100 #define LUN_4_EN 0
00101 #endif
00102 #if (LUN_5 == ENABLE)
00103 #define LUN_5_EN 1
00104 U8 code lun5_name[]=LUN_5_NAME;
00105 #else
00106 #define LUN_5_EN 0
00107 #endif
00108 #if (LUN_6 == ENABLE)
00109 #define LUN_6_EN 1
00110 U8 code lun6_name[]=LUN_6_NAME;
00111 #else
00112 #define LUN_6_EN 0
00113 #endif
00114 #if (LUN_7 == ENABLE)
00115 #define LUN_7_EN 1
00116 U8 code lun7_name[]=LUN_7_NAME;
00117 #else
00118 #define LUN_7_EN 0
00119 #endif
00120 #if (LUN_USB == ENABLE)
00121 #define LUN_USB_EN 1
00122 U8 code lunusb_name[]=LUN_USB_NAME;
00123 #else
00124 #define LUN_USB_EN 0
00125 #endif
00126
00127
00128 #define LUN_ID_0 (0)
00129 #define LUN_ID_1 (LUN_0_EN)
00130 #define LUN_ID_2 (LUN_0_EN+LUN_1_EN)
00131 #define LUN_ID_3 (LUN_0_EN+LUN_1_EN+LUN_2_EN)
00132 #define LUN_ID_4 (LUN_0_EN+LUN_1_EN+LUN_2_EN+LUN_3_EN)
00133 #define LUN_ID_5 (LUN_0_EN+LUN_1_EN+LUN_2_EN+LUN_3_EN+LUN_4_EN)
00134 #define LUN_ID_6 (LUN_0_EN+LUN_1_EN+LUN_2_EN+LUN_3_EN+LUN_4_EN+LUN_5_EN)
00135 #define LUN_ID_7 (LUN_0_EN+LUN_1_EN+LUN_2_EN+LUN_3_EN+LUN_4_EN+LUN_5_EN+LUN_6_EN)
00136 #define MAX_LUN (LUN_0_EN+LUN_1_EN+LUN_2_EN+LUN_3_EN+LUN_4_EN+LUN_5_EN+LUN_6_EN+LUN_7_EN)
00137 #define LUN_ID_USB (MAX_LUN)
00138
00139
00140 #if (MAX_LUN == 0)
00141 #error No memory is active in conf_access.h
00142 #endif
00143
00144
00145 #if (GLOBAL_WR_PROTECT == ENABLED)
00146 static U8 g_u8_wr_protect;
00147 #endif
00148
00149
00150
00151
00152
00157 U8 get_nb_lun()
00158 {
00159 #if (MEM_USB == ENABLED)
00160 return (MAX_LUN + Host_getlun());
00161 #else
00162 return MAX_LUN;
00163 #endif
00164 }
00165
00166
00171 U8 get_cur_lun()
00172 {
00173 return 0;
00174 }
00175
00176
00190 Ctrl_status mem_test_unit_ready( U8 lun )
00191 {
00192 switch( lun )
00193 {
00194 # if (LUN_0 == ENABLE)
00195 case LUN_ID_0:
00196 return Lun_0_test_unit_ready();
00197 break;
00198 # endif
00199 # if (LUN_1 == ENABLE)
00200 case LUN_ID_1:
00201 return Lun_1_test_unit_ready();
00202 break;
00203 # endif
00204 # if (LUN_2 == ENABLE)
00205 case LUN_ID_2:
00206 return Lun_2_test_unit_ready();
00207 break;
00208 # endif
00209 # if (LUN_3 == ENABLE)
00210 case LUN_ID_3:
00211 return Lun_3_test_unit_ready();
00212 break;
00213 # endif
00214 # if (LUN_4 == ENABLE)
00215 case LUN_ID_4:
00216 return Lun_4_test_unit_ready();
00217 break;
00218 # endif
00219 # if (LUN_5 == ENABLE)
00220 case LUN_ID_5:
00221 return Lun_5_test_unit_ready();
00222 break;
00223 # endif
00224 # if (LUN_6 == ENABLE)
00225 case LUN_ID_6:
00226 return Lun_6_test_unit_ready();
00227 break;
00228 # endif
00229 # if (LUN_7 == ENABLE)
00230 case LUN_ID_7:
00231 return Lun_7_test_unit_ready();
00232 break;
00233 # endif
00234 # if (LUN_USB == ENABLE)
00235 default:
00236 return Lun_usb_test_unit_ready(lun - LUN_ID_USB);
00237 break;
00238 # endif
00239 }
00240 return CTRL_FAIL;
00241 }
00242
00252 Ctrl_status mem_read_capacity( U8 lun , U32 _MEM_TYPE_SLOW_ *u32_nb_sector )
00253 {
00254 switch( lun )
00255 {
00256 # if (LUN_0 == ENABLE)
00257 case LUN_ID_0:
00258 return Lun_0_read_capacity( u32_nb_sector );
00259 break;
00260 # endif
00261 # if (LUN_1 == ENABLE)
00262 case LUN_ID_1:
00263 return Lun_1_read_capacity( u32_nb_sector );
00264 break;
00265 # endif
00266 # if (LUN_2 == ENABLE)
00267 case LUN_ID_2:
00268 return Lun_2_read_capacity( u32_nb_sector );
00269 break;
00270 # endif
00271 # if (LUN_3 == ENABLE)
00272 case LUN_ID_3:
00273 return Lun_3_read_capacity( u32_nb_sector );
00274 break;
00275 # endif
00276 # if (LUN_4 == ENABLE)
00277 case LUN_ID_4:
00278 return Lun_4_read_capacity( u32_nb_sector );
00279 break;
00280 # endif
00281 # if (LUN_5 == ENABLE)
00282 case LUN_ID_5:
00283 return Lun_5_read_capacity( u32_nb_sector );
00284 break;
00285 # endif
00286 # if (LUN_6 == ENABLE)
00287 case LUN_ID_6:
00288 return Lun_6_read_capacity( u32_nb_sector );
00289 break;
00290 # endif
00291 # if (LUN_7 == ENABLE)
00292 case LUN_ID_7:
00293 return Lun_7_read_capacity( u32_nb_sector );
00294 break;
00295 # endif
00296 # if (LUN_USB == ENABLE)
00297 default:
00298 return Lun_usb_read_capacity( lun - LUN_ID_USB,u32_nb_sector );
00299 break;
00300 # endif
00301 }
00302 return CTRL_FAIL;
00303 }
00304
00314 Bool mem_wr_protect( U8 lun )
00315 {
00316 switch( lun )
00317 {
00318 # if (LUN_0 == ENABLE)
00319 case LUN_ID_0:
00320 return Lun_0_wr_protect();
00321 break;
00322 # endif
00323 # if (LUN_1 == ENABLE)
00324 case LUN_ID_1:
00325 return Lun_1_wr_protect();
00326 break;
00327 # endif
00328 # if (LUN_2 == ENABLE)
00329 case LUN_ID_2:
00330 return Lun_2_wr_protect();
00331 break;
00332 # endif
00333 # if (LUN_3 == ENABLE)
00334 case LUN_ID_3:
00335 return Lun_3_wr_protect();
00336 break;
00337 # endif
00338 # if (LUN_4 == ENABLE)
00339 case LUN_ID_4:
00340 return Lun_4_wr_protect();
00341 break;
00342 # endif
00343 # if (LUN_5 == ENABLE)
00344 case LUN_ID_5:
00345 return Lun_5_wr_protect();
00346 break;
00347 # endif
00348 # if (LUN_6 == ENABLE)
00349 case LUN_ID_6:
00350 return Lun_6_wr_protect();
00351 break;
00352 # endif
00353 # if (LUN_7 == ENABLE)
00354 case LUN_ID_7:
00355 return Lun_7_wr_protect();
00356 break;
00357 # endif
00358 # if (LUN_USB == ENABLE)
00359 default:
00360 return Lun_usb_wr_protect(lun - LUN_ID_USB);
00361 break;
00362 # endif
00363 }
00364 return CTRL_FAIL;
00365 }
00366
00367
00374 Bool mem_removal( U8 lun )
00375 {
00376 switch( lun )
00377 {
00378 # if (LUN_0 == ENABLE)
00379 case LUN_ID_0:
00380 return Lun_0_removal();
00381 break;
00382 # endif
00383 # if (LUN_1 == ENABLE)
00384 case LUN_ID_1:
00385 return Lun_1_removal();
00386 break;
00387 # endif
00388 # if (LUN_2 == ENABLE)
00389 case LUN_ID_2:
00390 return Lun_2_removal();
00391 break;
00392 # endif
00393 # if (LUN_3 == ENABLE)
00394 case LUN_ID_3:
00395 return Lun_3_removal();
00396 break;
00397 # endif
00398 # if (LUN_4 == ENABLE)
00399 case LUN_ID_4:
00400 return Lun_4_removal();
00401 break;
00402 # endif
00403 # if (LUN_5 == ENABLE)
00404 case LUN_ID_5:
00405 return Lun_5_removal();
00406 break;
00407 # endif
00408 # if (LUN_6 == ENABLE)
00409 case LUN_ID_6:
00410 return Lun_6_removal();
00411 break;
00412 # endif
00413 # if (LUN_7 == ENABLE)
00414 case LUN_ID_7:
00415 return Lun_7_removal();
00416 break;
00417 # endif
00418 # if (LUN_USB == ENABLE)
00419 default:
00420 return Lun_usb_removal();
00421 break;
00422 # endif
00423 }
00424 return CTRL_FAIL;
00425 }
00426
00433 U8 code* mem_name( U8 lun )
00434 {
00435 switch( lun )
00436 {
00437 # if (LUN_0 == ENABLE)
00438 case LUN_ID_0:
00439 return (U8 code*)lun0_name;
00440 break;
00441 # endif
00442 # if (LUN_1 == ENABLE)
00443 case LUN_ID_1:
00444 return (U8 code*)lun1_name;
00445 break;
00446 # endif
00447 # if (LUN_2 == ENABLE)
00448 case LUN_ID_2:
00449 return (U8 code*)lun2_name;
00450 break;
00451 # endif
00452 # if (LUN_3 == ENABLE)
00453 case LUN_ID_3:
00454 return (U8 code*)lun3_name;
00455 break;
00456 # endif
00457 # if (LUN_4 == ENABLE)
00458 case LUN_ID_4:
00459 return (U8 code*)lun4_name;
00460 break;
00461 # endif
00462 # if (LUN_5 == ENABLE)
00463 case LUN_ID_5:
00464 return (U8 code*)lun5_name;
00465 break;
00466 # endif
00467 # if (LUN_6 == ENABLE)
00468 case LUN_ID_6:
00469 return (U8 code*)lun6_name;
00470 break;
00471 # endif
00472 # if (LUN_7 == ENABLE)
00473 case LUN_ID_7:
00474 return (U8 code*)lun7_name;
00475 break;
00476 # endif
00477 # if (LUN_USB == ENABLE)
00478 default:
00479 return (U8 code*)lunusb_name;
00480 break;
00481 # endif
00482 }
00483 return 0;
00484 }
00485
00486
00488
00489
00490
00502 Ctrl_status memory_2_usb( U8 lun , U32 addr , U16 nb_sector )
00503 {
00504 Ctrl_status status;
00505
00506 switch( lun )
00507 {
00508 # if (LUN_0 == ENABLE)
00509 case LUN_ID_0:
00510 status = Lun_0_read_10(addr , nb_sector);
00511 if (CTRL_GOOD == status)
00512 {
00513 status = Lun_0_usb_read();
00514 }
00515 break;
00516 # endif
00517 # if (LUN_1 == ENABLE)
00518 case LUN_ID_1:
00519 status = Lun_1_read_10(addr , nb_sector);
00520 if (CTRL_GOOD == status)
00521 {
00522 status = Lun_1_usb_read();
00523 }
00524 break;
00525 # endif
00526 # if (LUN_2 == ENABLE)
00527 case LUN_ID_2:
00528 status = Lun_2_read_10(addr , nb_sector);
00529 if (CTRL_GOOD == status)
00530 {
00531 status = Lun_2_usb_read();
00532 }
00533 break;
00534 # endif
00535 # if (LUN_3 == ENABLE)
00536 case LUN_ID_3:
00537 status = Lun_3_read_10(addr , nb_sector);
00538 if (CTRL_GOOD == status)
00539 {
00540 status = Lun_3_usb_read();
00541 }
00542 break;
00543 # endif
00544 # if (LUN_4 == ENABLE)
00545 case LUN_ID_4:
00546 status = Lun_4_read_10(addr , nb_sector);
00547 if (CTRL_GOOD == status)
00548 {
00549 status = Lun_4_usb_read();
00550 }
00551 break;
00552 # endif
00553 # if (LUN_5 == ENABLE)
00554 case LUN_ID_5:
00555 status = Lun_5_read_10(addr , nb_sector);
00556 if (CTRL_GOOD == status)
00557 {
00558 status = Lun_5_usb_read();
00559 }
00560 break;
00561 # endif
00562 # if (LUN_6 == ENABLE)
00563 case LUN_ID_6:
00564 status = Lun_6_read_10(addr , nb_sector);
00565 if (CTRL_GOOD == status)
00566 {
00567 status = Lun_6_usb_read();
00568 }
00569 break;
00570 # endif
00571 # if (LUN_7 == ENABLE)
00572 case LUN_ID_7:
00573 status = Lun_7_read_10(addr , nb_sector);
00574 if (CTRL_GOOD == status)
00575 {
00576 status = Lun_7_usb_read();
00577 }
00578 break;
00579 # endif
00580 }
00581 return status;
00582 }
00583
00595 Ctrl_status usb_2_memory( U8 lun , U32 addr , U16 nb_sector )
00596 {
00597 Ctrl_status status;
00598
00599 switch( lun )
00600 {
00601 # if (LUN_0 == ENABLE)
00602 case LUN_ID_0:
00603 status = Lun_0_write_10(addr , nb_sector);
00604 if (CTRL_GOOD == status)
00605 {
00606 status = Lun_0_usb_write();
00607 }
00608 break;
00609 # endif
00610 # if (LUN_1 == ENABLE)
00611 case LUN_ID_1:
00612 status = Lun_1_write_10(addr , nb_sector);
00613 if (CTRL_GOOD == status)
00614 {
00615 status = Lun_1_usb_write();
00616 }
00617 break;
00618 # endif
00619 # if (LUN_2 == ENABLE)
00620 case LUN_ID_2:
00621 status = Lun_2_write_10(addr , nb_sector);
00622 if (CTRL_GOOD == status)
00623 {
00624 status = Lun_2_usb_write();
00625 }
00626 break;
00627 # endif
00628 # if (LUN_3 == ENABLE)
00629 case LUN_ID_3:
00630 status = Lun_3_write_10(addr , nb_sector);
00631 if (CTRL_GOOD == status)
00632 {
00633 status = Lun_3_usb_write();
00634 }
00635 break;
00636 # endif
00637 # if (LUN_4 == ENABLE)
00638 case LUN_ID_4:
00639 status = Lun_4_write_10(addr , nb_sector);
00640 if (CTRL_GOOD == status)
00641 {
00642 status = Lun_4_usb_write();
00643 }
00644 break;
00645 # endif
00646 # if (LUN_5 == ENABLE)
00647 case LUN_ID_5:
00648 status = Lun_5_write_10(addr , nb_sector);
00649 if (CTRL_GOOD == status)
00650 {
00651 status = Lun_5_usb_write();
00652 }
00653 break;
00654 # endif
00655 # if (LUN_6 == ENABLE)
00656 case LUN_ID_6:
00657 status = Lun_6_write_10(addr , nb_sector);
00658 if (CTRL_GOOD == status)
00659 {
00660 status = Lun_6_usb_write();
00661 }
00662 break;
00663 # endif
00664 # if (LUN_7 == ENABLE)
00665 case LUN_ID_7:
00666 status = Lun_7_write_10(addr , nb_sector);
00667 if (CTRL_GOOD == status)
00668 {
00669 status = Lun_7_usb_write();
00670 }
00671 break;
00672 # endif
00673 }
00674 return status;
00675 }
00676
00678 #if (ACCESS_MEM_TO_RAM == ENABLED)
00679
00689 Ctrl_status memory_2_ram( U8 lun , const U32 _MEM_TYPE_SLOW_ *addr , U8 _MEM_TYPE_SLOW_ *ram )
00690 {
00691
00692 Ctrl_status status;
00693
00694 switch( lun )
00695 {
00696 # if (LUN_0 == ENABLE)
00697 case LUN_ID_0:
00698 status = Lun_0_mem_2_ram(*addr , ram);
00699 if (CTRL_GOOD == status)
00700 {
00701 status = Lun_0_mem_2_ram_read();
00702 }
00703 break;
00704 # endif
00705 # if (LUN_1 == ENABLE)
00706 case LUN_ID_1:
00707 status = Lun_1_mem_2_ram(*addr , ram);
00708 if (CTRL_GOOD == status)
00709 {
00710 status = Lun_1_mem_2_ram_read();
00711 }
00712 break;
00713 # endif
00714 # if (LUN_2 == ENABLE)
00715 case LUN_ID_2:
00716 status = Lun_2_mem_2_ram(*addr , ram);
00717 if (CTRL_GOOD == status)
00718 {
00719 status = Lun_2_mem_2_ram_read();
00720 }
00721 break;
00722 # endif
00723 # if (LUN_3 == ENABLE)
00724 case LUN_ID_3:
00725 status = Lun_3_mem_2_ram(*addr , ram);
00726 if (CTRL_GOOD == status)
00727 {
00728 status = Lun_3_mem_2_ram_read();
00729 }
00730 break;
00731 # endif
00732 # if (LUN_4 == ENABLE)
00733 case LUN_ID_4:
00734 status = Lun_4_mem_2_ram(*addr , ram);
00735 if (CTRL_GOOD == status)
00736 {
00737 status = Lun_4_mem_2_ram_read();
00738 }
00739 break;
00740 # endif
00741 # if (LUN_5 == ENABLE)
00742 case LUN_ID_5:
00743 status = Lun_5_mem_2_ram(*addr , ram);
00744 if (CTRL_GOOD == status)
00745 {
00746 status = Lun_5_mem_2_ram_read();
00747 }
00748 break;
00749 # endif
00750 # if (LUN_6 == ENABLE)
00751 case LUN_ID_6:
00752 status = Lun_6_mem_2_ram(*addr , ram);
00753 if (CTRL_GOOD == status)
00754 {
00755 status = Lun_6_mem_2_ram_read();
00756 }
00757 break;
00758 # endif
00759 # if (LUN_7 == ENABLE)
00760 case LUN_ID_7:
00761 status = Lun_7_mem_2_ram(*addr , ram);
00762 if (CTRL_GOOD == status)
00763 {
00764 status = Lun_7_mem_2_ram_read();
00765 }
00766 break;
00767 # endif
00768 # if (LUN_USB == ENABLE)
00769 default:
00770 return Lun_usb_mem_2_ram(*addr , ram);
00771 # endif
00772 }
00773 return status;
00774 }
00775 #endif // ACCESS_MEM_TO_RAM == ENABLED
00776
00777
00778
00779 #if (ACCESS_MEM_TO_RAM==ENABLE)
00780
00790 Ctrl_status ram_2_memory( U8 lun , const U32 _MEM_TYPE_SLOW_ *addr , U8 _MEM_TYPE_SLOW_ * ram )
00791 {
00792 Ctrl_status status;
00793
00794 switch( lun )
00795 {
00796 # if (LUN_0 == ENABLE)
00797 case LUN_ID_0:
00798 status = Lun_0_ram_2_mem(*addr , ram);
00799 if (CTRL_GOOD == status)
00800 {
00801 status = Lun_0_ram_2_mem_write();
00802 }
00803 break;
00804 # endif
00805 # if (LUN_1 == ENABLE)
00806 case LUN_ID_1:
00807 status = Lun_1_ram_2_mem(*addr , ram);
00808 if (CTRL_GOOD == status)
00809 {
00810 status = Lun_1_ram_2_mem_write();
00811 }
00812 break;
00813 # endif
00814 # if (LUN_2 == ENABLE)
00815 case LUN_ID_2:
00816 status = Lun_2_ram_2_mem(*addr , ram);
00817 if (CTRL_GOOD == status)
00818 {
00819 status = Lun_2_ram_2_mem_write();
00820 }
00821 break;
00822 # endif
00823 # if (LUN_3 == ENABLE)
00824 case LUN_ID_3:
00825 status = Lun_3_ram_2_mem(*addr , ram);
00826 if (CTRL_GOOD == status)
00827 {
00828 status = Lun_3_ram_2_mem_write();
00829 }
00830 break;
00831 # endif
00832 # if (LUN_4 == ENABLE)
00833 case LUN_ID_4:
00834 status = Lun_4_ram_2_mem(*addr , ram);
00835 if (CTRL_GOOD == status)
00836 {
00837 status = Lun_4_ram_2_mem_write();
00838 }
00839 break;
00840 # endif
00841 # if (LUN_5 == ENABLE)
00842 case LUN_ID_5:
00843 status = Lun_5_ram_2_mem(*addr , ram);
00844 if (CTRL_GOOD == status)
00845 {
00846 status = Lun_5_ram_2_mem_write();
00847 }
00848 break;
00849 # endif
00850 # if (LUN_6 == ENABLE)
00851 case LUN_ID_6:
00852 status = Lun_6_ram_2_mem(*addr , ram);
00853 if (CTRL_GOOD == status)
00854 {
00855 status = Lun_6_ram_2_mem_write();
00856 }
00857 break;
00858 # endif
00859 # if (LUN_7 == ENABLE)
00860 case LUN_ID_7:
00861 status = Lun_7_ram_2_mem(*addr , ram);
00862 if (CTRL_GOOD == status)
00863 {
00864 status = Lun_7_ram_2_mem_write();
00865 }
00866 break;
00867 # endif
00868 # if (LUN_USB == ENABLE)
00869 default:
00870 return Lun_usb_ram_2_mem(*addr , ram);
00871 break;
00872 # endif
00873 }
00874 return status;
00875 }
00876 #endif // ACCESS_RAM_TO_MEM == ENABLED
00877
00878
00879
00881 #if (ACCESS_STREAM == ENABLED)
00882
00883
00884
00885
00886 # if (ACCESS_MEM_TO_MEM == ENABLED)
00892 U8 stream_mem_to_mem( U8 src_lun , U32 src_addr , U8 dest_lun , U32 dest_addr , U16 nb_sector )
00893 {
00894 while(nb_sector)
00895 {
00896 memory_2_ram( src_lun , &src_addr , buf_sector );
00897 ram_2_memory( dest_lun , &dest_addr , buf_sector );
00898 src_addr++;
00899 dest_addr++;
00900 nb_sector--;
00901 }
00902 return CTRL_GOOD;
00903 }
00904 # endif // ACCESS_MEM_TO_MEM == ENABLED
00905
00906
00907
00908
00918 Ctrl_status stream_state( U8 Id )
00919 {
00920
00921 return CTRL_GOOD;
00922 }
00923
00930 U16 stream_stop( U8 Id )
00931 {
00932 return 0;
00933 }
00934
00935 #endif // ACCESS_STREAM == ENABLED